1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors and used for generating a different type of strain in channel regions of different transistor types.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used, due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
During the formation of the two types of stressed layers, conventional techniques, also referred to as dual stress liner approaches, may suffer from reduced efficiency when device dimensions are increasingly scaled by using the 45 nm technology and even further advanced approaches, due to the limited conformal deposition capabilities of the deposition processes involved, which may result in respective process non-uniformities during subsequent process steps for patterning the stressed layer and forming contact openings, as will be explained in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a top view of a semiconductor device 100 comprising a first device region 120A and a second device region 120B. The first and second device regions 120A, 120B may represent device regions in which closely spaced transistor elements have to be formed, which may comprise gate electrodes 121 in the form of conductive polysilicon lines, which may extend above a semiconductor layer 102 which may, for instance, at the first device region 120A, represent the active regions for P-channel transistors, while the semiconductor layer 102 may represent an N-active region in the device region 120B. The gate electrode structures 121 may also extend above an isolation region 103, for instance in the form of an appropriate dielectric material, such as silicon dioxide and the like, which may also be indicated as a field region.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 in a certain manufacturing stage for forming stress-inducing layers above the first device area 120A and the second device area 120B. The cross-sectional view is taken along the line Ib-Ib of FIG. 1a and hence the specific transistor configuration within the semiconductor layer is not illustrated, since, according to the cross-section of FIG. 1b, the gate electrodes are shown above the isolation structure 103. The first and second device areas 120A, 120B, which typically represent respective transistor elements, may be formed above a substrate 101 comprising the semiconductor layer 102, such as a silicon-based layer, which may be separated from a substrate 101 by an appropriate buried insulating layer (not shown) if a silicon-on-insulator (SOI) configuration is considered. In the example shown, the first and second device areas 120A, 120B may comprise a plurality of transistor elements with a lateral distance according to the design rules of the technology under consideration. The transistors in the first and second device areas 120A, 120B may comprise the gate electrodes 121 formed on respective gate insulation layers (not shown), which separate the gate electrodes 121 from a corresponding channel region in the semiconductor layer 102, which is laterally located between respective drain/source regions. Furthermore, a sidewall spacer structure 122 may be formed on sidewalls of the gate electrode 121. Typically, metal silicide regions (not shown) may be provided in the drain and source regions and the gate electrodes 121 in order to enhance the conductivity of these areas. Furthermore, the isolation region or field region 103 may be recessed in the region 120B and to a lesser degree also in the region 120A, as indicated by 103B, 103A, respectively. The semiconductor device 100 may represent an advanced device, in which critical dimensions, such as the gate length, i.e., in FIG. 1b, the horizontal extension of the gate electrodes 121, may be approximately 50 nm or significantly less. Consequently, a distance between respective transistor elements, i.e., the lateral distance between neighboring sidewall spacer structures 122 of closely spaced gate electrodes 121, as shown in the device region 120B, may be approximately 100 nm or even less.
Furthermore, in the manufacturing stage shown in FIG. 1b, a silicon nitride layer 130, comprising, for instance, a high intrinsic tensile stress, is formed above the first and second device areas 120A, 120B, followed by an etch stop layer 131 comprised of silicon dioxide. It should be appreciated that, if required, an etch stop layer 133, such as a silicon dioxide layer of appropriate thickness and density, may be provided between the silicon nitride layer 130 and the respective transistor elements in the first and second device areas 120A, 120B. The etch stop layer 131 is typically provided with a thickness that is sufficient to stop an etch process in a later stage when patterning the layer 130, or to provide a pronounced endpoint detection signal. That is, a silicon nitride etch chemistry reacting with silicon dioxide results in a specific plasma ambient that can be detected by standard detection techniques. Usually, a thickness of the etch indicator layer 131 is selected to be approximately 20 nm or more, thereby providing sufficient etch stop capabilities across the substrate in order to reliably control the respective etch process. In some approaches, the etch indicator layer 131 may act as a hard mask during the patterning of the silicon nitride layer 130.
As is evident from FIG. 1b, due to the reduced spacing between neighboring gate electrodes, and thus transistor elements, above the semiconductor layer and the recesses 103B, 103A, the silicon nitride layer 130 may have to be deposited on the basis of a pronounced aspect ratio, in particular in the second region 120B due to the recess 103B.
Furthermore, in this manufacturing stage, the semiconductor device 100 may comprise a resist mask 104 exposing the second device area 120B, while covering the first device region 120A. In this case, it may be assumed that the intrinsic stress of the silicon nitride layer 130 may be appropriately selected so as to enhance the transistor performance in the first device area 120A, which in the present example represents an N-region.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1b may comprise the following processes. The gate electrodes 121 and the gate insulation layers may be formed and patterned on the basis of well-established process techniques, including advanced photolithography, deposition, oxidation and etch techniques.
As previously explained, in sophisticated applications, strain-inducing mechanisms may be implemented, for instance, in the form of a silicon germanium material provided in drain and source areas in a strained state, thereby also inducing a corresponding compressive strain in the adjacent channel region of P-channel transistors. Thus, in some cases, the N-region 120A may be covered by an appropriate etch mask while the P-region 120B may obtain appropriate sidewall spacer elements after forming the gate electrode in order to determine an offset of cavities to be etched into the semiconductor layer 102 in the region 120B. During the corresponding patterning process, material of the isolation structure 103 may be removed, thereby increasingly forming the recess 103B, which may further be deepened by the etch processes, cleaning processes and the like, which may also create the recess 103A in the first device region 120A.
Thereafter, the drain and source regions may be formed in combination with the sidewall spacer structures 122 on the basis of well-established deposition, anisotropic etch processes and implantation sequences in order to establish the desired vertical and lateral dopant profile. Thereafter, respective silicide regions may be formed, if required, on the basis of well-established techniques. Next, if required, a corresponding silicon dioxide etch stop layer may be formed, followed by the deposition of the silicon nitride layer 130. During the deposition of the silicon nitride material, respective process parameters, such as composition of carrier gases and reactive gases, substrate temperature, deposition pressure and in particular ion bombardment during the deposition, may significantly influence the finally obtained intrinsic stress of the material as deposited with respect to the underlying materials. Thus, by selecting appropriate parameter values, a high degree of intrinsic stress, such as up to 2 Gigapascal (GPa) and even more of compressive stress or up to 1 GPa or even significantly higher of tensile stress, may be created so as to enhance the performance of the transistor in the first device area 120A. Due to the less pronounced conformality of the silicon nitride deposition process above a certain layer thickness and for increased aspect ratios, as may be encountered in particular above the isolation region 103 of highly scaled devices caused by the reduced distance between the neighboring transistor elements at moderately dimensioned gate heights and the recesses 103B, 103A, as shown, the thickness of the silicon nitride material is selected so as to avoid irregularities, such as voids.
After the deposition of the silicon dioxide layer 131, the resist mask 104 may be formed on the basis of well-established photolithography techniques. Next, an appropriately designed etch process may be performed in order to remove a portion of the layers 130 and 131 from the device area 120B. During the corresponding etch process, the silicon dioxide material of the layer 131 may be removed first followed by a selective etch process for removing the material of the silicon nitride layer 130, wherein the corresponding etch process may be controlled on the basis of the etch stop layer 133.
FIG. 1c schematically illustrates the semiconductor device 100 at a further advanced manufacturing stage. As shown, a second dielectric layer 140 may be formed above the first and second device areas 120A, 120B, wherein a void 132 may be present in the second device area 120B due to the limited gap filling capability of the deposition process for forming a highly stressed silicon nitride material and the pronounced surface topography. The void 132 in the second device region 120B may result in degraded etch uniformity during the subsequent processing, thereby resulting in a significant yield loss. For example, in a later stage, contacts may have to be formed that connect to a portion of the gate electrodes 121 positioned above the isolation or field regions 103 and also to drain and source regions formed in the active regions enclosed by the isolation region 103. In this common patterning sequence, the void 132 may thus contribute to significant yield losses due to non-reliable contacts, short circuits between the drain or source region and the channel region, and the like.
Furthermore, at the manufacturing stage shown in FIG. 1c, a corresponding resist mask 104A is provided to protect the dielectric layer 140 during a corresponding etch process for removing the exposed portion of the layer 140 in the first device region 120A.
With respect to the formation of the second dielectric layer 140, substantially the same criteria apply as previously explained with respect to the layer 130. Hence, during the deposition of the layer 140, respective process parameters may be adjusted in an appropriate manner so that a desired high intrinsic stress may be obtained.
FIG. 1d schematically illustrates the device 100 at a further advanced manufacturing stage, wherein a corresponding interlayer dielectric material 150, for instance comprised of silicon dioxide, may be formed above the first and second dielectric layers 130, 140. The dielectric material 150 may be formed on the basis of well-established techniques, such as sub-atmospheric deposition processes on the basis of TEOS, plasma assisted chemical vapor deposition (CVD) and the like, which may be followed by respective planarization processes, if required. Thereafter, respective contact openings may be formed, which may, in some cases, for instance in dense SRAM regions, connect to the device layer at areas located between respective closely spaced transistors and which may also extend into the isolation region 103. Thus, the corresponding voids 132 may affect the corresponding process, thereby resulting in less reliable contacts or even total contact failures, which may represent a major contribution to the overall yield losses during the fabrication of devices of the 45 nm technology.
As a consequence, upon further device scaling, the respective limitation of deposition processes for dielectric materials of high intrinsic stress may require a significant reduction of the layer thickness of the stress-inducing layers to comply with increased aspect ratios encountered in advanced device geometries. However, in this case, the respective strain induced by the stressed dielectric materials may also be significantly reduced, thereby also reducing transistor performance.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.